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Overview
The Interconnect Focus Center (IFC) conducts research to discover and invent new electrical, optical and thermal interconnect solutions that will meet or exceed ITRS projections and enable hyper-integration of heterogeneous components for future terascale systems.
The IFC was founded in 1998 to research all aspects of the wiring that connect the millions of transistors on a microchip, from process to system-level architecture. Today and in the future, the microelectronics and nanotechnology industries will lead the evolution of technology in industries from automotive to medical, and from computing to aviation. The IFC strives to stay atop all advances in these fields and play a major role in driving this technology into the future. To that end, the center's research themes have evolved to accommodate this goal.
Research Focus
Exacerbating factors pertaining to the copper-based interconnect schemes for use in future sub-50 nanometer generations of silicon technology drive the need to invent new interconnect solutions. The research focus in the IFC is to discover and invent electrical, optical and thermal interconnect solutions that enable hyper-integration of heterogeneous components. The approach is to capitalize on the enormous amount of research being conducted in nanoscience and technology to develop novel high conductance electrical interconnects to replace copper. Our research also identifies and explores the opportunities and barriers for optical interconnects that will scale to meet the needs of future gigascale silicon electronic systems with emphasis on input/output and global on-chip interconnects.
Interconnect-driven circuit and system design, and modeling are investigated to understand the fundamental trade-offs between electrical and optical interconnections for short-haul communication. In view of the foreseen technology roadblocks of power delivery and thermal management, novel approaches in these areas will be explored.
Themes and Theme Drivers
Research in Interconnect addresses the following four Themes:
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Electrical Interconnects |
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Optical Interconnects |
III. |
Thermal Management and Power Delivery |
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Circuit and System Design and Modeling |
The center is also pursuing two Design Drivers:
I. |
Futuristic high performance, hypothetical, network routing/computing chip which stresses interconnects to the extreme |
| II. |
Consists of integrated nano-scale non-metallic conductors and devices built on a CMOS platform. |
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Save these Dates |
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Electronic Seminars
Thursdays @ 4PM ET |
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Michal Lipson:TBD |
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Yogi Joshi and Andrei Fedorov: Integrated Chip Level
Solutions for Hot Spot Thermal Management in the Presence of
Significant Background Heat Fluxes |
Apr 10 |
Saroj Nayak: First Principal Study of Electron and Spin Transport in Copper Wires, Carbon Nanotubes and Graphenes: From Electrons to Interconnects |
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David Miller: Power-Efficient Optical Interconnects |
| May 1 |
Azad Naeemi: Performance Modeling for Graphene Nanoribbon Interconnects |
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Carl Thompson: Potential Benefits and Technological Hurdles for CNT Interconnects |
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Serge Oktyabrsky: Novel Concepts of Fast Photonic Sources for
Off-Chip Interconnects |
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Pulickel Ajayan: Carbon-Based Interconnects: Nanotubes, Graphenes, and
Beyond |
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Rizwan Bashirullah: High Speed Electrical Interconnects |
Aug 7 |
Silvija Gradečak: TBD |
Aug 28 |
Sung Kyu Lim: TBD |
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Vladimir Stojanovic: The Interconnect Problem: From Emerging Devices to Energy-efficient Networks |
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Research Focus in the News |
IFC researchers demonstrate that nanotube wires operating at speed of commercial chips. |
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Chipmakers have hoped that carbon “nanotubes” would allow them to continue using thinner wiring as they pack more devices into chips. In a paper published online today by the journal Nano Letters, engineers at Stanford University report using nanotubes to wire a silicon chip operating at speeds comparable to those of commercially available processors and memory.
“This is the first time anyone has been able to show digital signals going through nanotubes at 1 gigahertz,” said H.-S. Philip Wong, a professor of electrical engineering at Stanford and a co-author of the report.
The advance shows that nanotubes are not only capable of connecting transistors at industrially relevant speed, but of doing so in real circuits that use materials, designs and manufacturing processes compatible with those that chipmakers use today, added Gael Close, an electrical engineering doctoral student and the paper’s lead author.
The silicon chip is an array of 256 circuits called “ring oscillators,” which are industry-standard circuits for testing the speed of chips. Including other control circuitry that allowed for selectively operating each of the 256 oscillators, the chip comprised a total of 11,000 transistors in an area one hundredth of a square inch.
For more information go here.
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People in the News |
| Muhannad Bakir |
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Best Invited Paper at
Custom Integrated Circuits Conference 2007:
"Revolutionary NanoSilicon
Ancillary Technologies for
Ultimate-Performance
Gigascale Systems" |
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| Pulickel Ajayan |
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University Makes New Black from Tiny Carbon Tubes
Listen to Melissa Block from
All Things Considered interview
Pulickel Ajayan on the "New Black." |
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